Static induction transistor

Abstract

A static induction transistor of the type wherein carriers are injected from a source to a drain across a potential barrier induced in a current channel and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate and to a drain bias voltage applied to the drain to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R.sub.c and the true transconductance G.sub.m of the transistor is maintained less than one and the product of the true transconductance and the series resistance R.sub.s of the transistor is maintained greater than or equal to one in the low drain current region in the operative state of the transistor. The series resistance R.sub.s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region. In an upside-down structure, the above-mentioned conditions can be easily attained by selecting respective impurity concentrations and thicknesses of a substrate and an epitaxial layer grown thereon.