Cpu employing micro programmable control for use in a data processing

Abstract

A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes. Data path connections provide for selective connection of the register file and the ALU output to the memory bus dependent upon existing memory bus and data bus communication with the memory. The above functions are accomplished with a fifty-six bit micro-instruction format implemented with a sixteen bit word length, which allows for a flexible instruction set for a microprogrammed processor enabling a system to be designed to span the range from a minicomputer to a large processor.