Self synchronizing clock derivation circuit for double frequency encoded

Abstract

A circuit for accurately reconstructing the timing information encoded within digital waveforms of the double frequency class includes facilities for restoring the circuit to proper synchronization at start up time or after a burst of noise on an incoming waveform. The circuit first generates three delayed versions of the incoming double frequency waveform. Transitions in the incoming waveform are detected by comparing the incoming waveform with the first delayed waveform and simultaneously comparing the second and third delayed waveforms, the generated transition-event waveforms being identical but out of phase by one half of the bit cell time of the incoming waveform. The two generated transition waveforms are used to form a composite clock which is then used to toggle the state of a D-type flip-flop at one half bit cell intervals. The Q and Q outputs of the flip-flop are then gated with the first and second transition waveforms to produce first and second clocking signals, the first clocking signal commencing at each guaranteed transition in the incoming waveform, the second clocking signal commencing one-half bit cell after each guaranteed transition in the incoming waveform. In order to assure that the flip-flop is properly synchronized with the incoming waveform, the incoming waveform is additionally compared with the identical incoming waveform delayed by one-half bit cell. The signal produced and the Q output of the flip-flop are inputted to a logical NAND, and the output of the NAND is fed to the flip-flop's D-input, thus assuring that the flip-flop is synchronized with the incoming waveform.