Bit synchronizer

Abstract

A bit synchronizer for T-4 fiber optic data communication environments is configured of an input buffer amplifier to which the data to be regenerated is applied. The input buffer provides isolation between upstream signal processing circuitry and a bit rate generator coupled to the output of the buffer. Also coupled to the buffer output is a bit decision circuit essentially configured of a limiter and output flip-flop. The bit rate generator employs a limiter and dual delay logic circuitry connected in series that provide a strong bit rate component which is phase coherent with the input NRZ data transitions. Unwanted baseband components are removed by a bandpass filter the output of which, as the output of the bit rate generator, is coupled to a phase locked loop from which a crystal oscillator clock synchronized with the data transitions is produced to clock the output flip-flop in the bit decision circuit. Interposed between the output of the crystal oscillator and the clock control input of the output flip-flop is a delay circuit which is set to adjust the clock timing to mid-bit of the limiter. The regenerated data is derived from the Q output of the flip-flop.