Double word fetch system

Abstract

A memory subsystem couples to a single word bus in common with a central processing unit for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which specifies the row of chips to be accessed within a first one of the pair of memory units. The subsystem further includes control circuits, common timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom. The control circuits, in response to each memory request which specifies a predetermined type of memory operation, condition the timing circuits to generate a sequence of timing signals for access and read out of the pair of words into a pair of tri-state operated data registers. The outputs of the data registers are connected in common and under the control of the timing circuits, the words are multiplexed onto the single word bus for transfer to the central processing unit over a corresponding number of successive bus cycles.