Method of controlling mosfet threshold voltage with self-aligned channel

Abstract

A process is provided for fabricating MOSFET devices having field source, gate and drain regions. The threshold voltage of both the channel and field regions of such devices is controlled by forming a comparatively thick oxide film on a semiconductor surface, defining enhancement mode transistor regions in the oxide film to expose portions of the semiconductor surface, implanting p-type ions under conditions such that the peak distribution of p-type atoms lies in the semi-conductor substrate just beneath the semiconductor/-oxide interface and counter-doping with n-type ions under conditions such that no implanted ions penetrate the oxide film. As a consequence, a desirably high threshold voltage is obtained in the field region, while a desirably low threshold voltage is obtained in the channel region. Depletion mode transistors are fabricated on the same wafer by masking the enhancement mode regions, defining depletion mode transistor regions in the oxide film to expose portions of the semiconductor surface and implanting n-type ions under conditions such that no ions penetrate the mask or oxide film. Metal gate or refractory gate technology is then employed to fabricate source, gate and drain regions and electrical contacts thereto. Parasitic conduction paths between neighboring transistors are substantially eliminated due to the peak distribution of p-type atoms in the field region.