Process for producing a calibrated resistance element and integrated

Abstract

Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.