Method of fabricating a charge transfer channel covered by a stepped

Abstract

The disclosed memory cell is comprised of a charge storage region and an adjacent charge transfer channel. A deep dopant layer extends throughout the charge storage region, and a shallow dopant layer extends throughout the charge storage region plus part-way through the charge transfer channel. Overlying the charge storage region is a first conductor that is completely covered by a thick insulating layer. This thick insulating layer also extends into the charge transfer channel part-way over the shallow dopant layer. A thin insulating layer covers the remaining portion of the channel. Lying on this thin insulating layer and extending onto the thick insulating layer is a second conductor. Parasitic capacitance and catastrophic shorts between the two conductors are minimized by the thick insulating layer; charge storage capacity of the storage region is maximized by the two dopant layers lying therein; and cell length is minimized by the thick insulating layer and underlying shallow dopant layer in the charge transfer channel.