Phase-locked loop frequency synthesizer including compensated phase and

Abstract

A phase-locked loop is disclosed that exhibits flat modulation characteristics over a wide range of carrier frequencies for either frequency or phase modulation at rates that are both within and outside the loop bandwidth. The disclosed arrangement is a programmable divide-by-N phase-locked loop frequency synthesizer wherein the feedback path includes a second phase-locked loop that serves as a tracking filter. Modulation is supplied to the main phase-locked loop via a first modulation path that couples the modulating signal to the frequency control terminal of the phase-locked loop voltage-controlled oscillator and via a second modulation path that couples the modulating signal to the phase-locked loop phase detector. To configure the system so that flat modulation is attained, the gain factors of the first and second modulation paths are established in accordance with specific relationships and the second modulation path includes a compensator network having a transfer function that at least aproximates that of the phase-locked loop which is embedded in the system feedback path. Additionally, the modulation signal coupled to both modulation paths is adjusted on the basis of carrier frequency to compensate for frequency-related variation in the transfer characteristics of the main loop VCO. The transfer characteristic of the main loop phase detector is controlled to maintain a constant loop bandwidth.