Clock derivation circuit for double frequency encoded serial digital data

Abstract

A circuit arrangement for extracting clocking signals from double frequency encoded transition-event waveforms. The incoming waveform is fed directly into a digital delay line which generates three versions of the incoming waveform, each delayed by 1/4, 1/2 and 3/4 of the incoming waveform's bit cell time, respectively. Transitions in the incoming waveform are detected by comparing the output of the first delay line tap with the incoming waveform and simultaneously comparing the outputs of the second and third delay line taps, thus generating first and second transition waveforms that are identical but out of phase by one-half bit cell. The two generated transition waveforms are used to form a composite clock which is then used to toggle a flip-flop at one-half bit cell intervals. The true and false outputs of the flip-flop are then gated with the first and second generated transition waveforms, respectively, to produce the two desired clocking signals, the first clocking signal providing pulses commencing at the incoming waveform's guaranteed transitions, the second clocking signal providing pulses commencing one-half bit cell after the incoming waveform's guaranteed transitions.