Logic test system permitting test pattern changes without dummy cycles

Abstract

A system for testing logical devices, in which a pattern file is used to store numerous test patterns, each of which includes both an input pattern, which is provided as an input to the device under test, and an expected value pattern, which is compared with the actual output of the device under test to ascertain whether malfunction has occurred. By accessing the pattern file at various addresses, different test patterns can selectively be applied to the device in a test. A command file includes instructions for controlling the sequence in which the various test patterns included in the pattern file are accessed, and an operand file includes data which may be required for carrying out the instructions contained in the command file. Index, stack point, and subroutine return registers are also used to execute the instructions which may be contained in the command file. In addition, provision of a mask data address file with associated structures permits similarly controlled selection of which terminals of the logical device under test are to be tested or disregarded. Thus, by executing a sequence of instructions which are stored in the command file, a very large number of possible test sequences can be executed, without ever interrupting the sequence of input patterns which are applied to the device under test.