Computer input/output arrangement for enabling a simultaneous read/write

Abstract

A computer input/output arrangement is disclosed which utilizes a rotate memory instruction of a computer instruction set for performing a bit by bit read/write data transfer between the computer memory and a connected peripheral device. The arrangement enables the rotate memory instruction to perform read and write steps simultaneously from memory and the peripheral device. During the read step data is simultaneously read from the memory location and the peripheral device into associated locations in a computer register. The register data is rotated such that the received data in the peripheral device bit location is rotated into the memory bit locations of the register while simultaneously rotating a memory data bit into the peripheral device bit location. The write step writes register data from the peripheral device bit location to the peripheral device while simultaneously writing the data from the memory bit locations into the memory.