Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device having a multi-layer wiring system includes the steps of providing a first pattern of conductive regions on a major surface, providing an intermediate conductive layer over the major surface and the first pattern conductive regions, providing a second pattern of conductive tracks on the intermediate layer, and selectively etching the intermediate layer using the second pattern of tracks as an etching mask to completely remove the intermediate layer by underetching below portions of the second pattern tracks crossing over portions of the first pattern of conductive region where no electrical interconnection between the first and second conductive patterns is desired, while only partially removing the intermediate layer by underetching below portions of the second pattern of tracks crossing over portion of the first pattern of semiconductor regions where an electrical interconnection between the first and second conductor patterns is desired. In this manner, at least two separate parts of the first pattern of conductive regions are conductively connected at selected locations by a part of the second pattern of tracks in a method in which the conductive tracks of the uppermost level are used at a self-aligning etching mask.