The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 1981
Filed:
Sep. 16, 1980
Sanford Lebow, Westlake Village, CA (US);
Daniel Nogavich, Newbury Park, CA (US);
Pactel Corporation, Newbury Park, CA (US);
Abstract
A printed circuit which may be highly flexible in configuration and design includes at least one uniformly thick, planar circuit layer including a conductive circuit pattern and an insulating circuit pattern of a cured, flowable insulating material. The printed circuit may include multiple circuit layers that are selectively electrically connected to other layers and may provide circuit patterns, mechanically supportive insulator patterns and windows in almost any desired configuration. The printed circuit may be bonded to a substrate in a high thermal transfer configuration, implemented as a film carrier having plated conductors extending from the surface to receive directly pads of integrated circuit chips or used as a high strength, low coefficient of thermal expansion flexible cable. The printed circuit is manufactured by forming a first conductive circuit pattern on a polished temporary substrate, forming a second conductive circuit pattern (which may be an interconnect pattern) on the first pattern if desired, laminating a flowable insulator material to the first and second conductive circuit layers and temporary substrate to form first and second insulator layers, sanding to form a smooth top surface coplanar with the top of the top conductive pattern, selectively adding additional layers and a substrate and stripping the printed circuit from the temporary substrate. The conductive patterns may be formed with high resolution using photolithographic techniques.