Differential charge sensing system

Abstract

A sensing system is provided for a memory cell having first and second transistors with first and second diffusion capacitances, respectively, storing unequal amounts of charge which are coupled to first and second bit lines, respectively. The cell is preferably a four device integrated injection logic or merged transistor logic bipolar cell. The charges represent stored information and are maintained in a standby condition by maintaining a charge on the bit lines. When the information is to be sensed, the bit lines are discharged through the cell to enhance the charge difference in the diffusion capacitances. The charge now stored in the diffusion capacitances is transferred onto the bit lines and detected by a differential sensing circuit connected between the first and second bit lines to which are connected first and second equal valued resistors, respectively. The charge in the diffusion capacitances which results after enhancement may be transferred onto the bit lines by discharging the bit lines through the two resistors or by pulsing up the diffusion capacitances from a terminal remote from the bit lines to force the charge onto the bit lines.