The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 1981
Filed:
Jan. 05, 1979
Applicant:
Inventors:
Daniel C Guterman, Houston, TX (US);
Te-Long Chiu, Houston, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; B01J / ;
U.S. Cl.
CPC ...
357 41 ; 357 23 ; 357 45 ; 357 51 ; 357 59 ; 2957 / ; 2957 / ; 29578 ;
Abstract
A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.
Guterman, Daniel. (1981). Self-limiting erasable memory cell with triple level polysilicon (U.S. Patent No. 4302766). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4302766
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile