The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 1981
Filed:
Apr. 24, 1979
John H Cutler, Roanoke, VA (US);
Loren H Walker, Salem, VA (US);
General Electric Company, Salem, VA (US);
Abstract
A fixed gating sequence apparatus and method for an inverter is disclosed. In one aspect of the invention, an outgoing signal of variable frequency is generated by the inverter in response to gating signals provided by an inverter control. The gating signals effectively are provided by a shift register of an inverter control to the gates of the conduction controlled rectifying devices in the inverter in response to a clocking signal. The clocking signal is provided to the clock input of the shift register at a normal system rate when an idle condition (idle control signal) is not present and at a predetermined cycling rate from when the idle condition occurs until a desired fixed gating pattern effectively is provided by the shift register to the inverter. The shift register remains at the stage providing the desired fixed gating pattern until the idle condition no longer is present, whereupon the normal clocking signals are again provided to the shift register. In another aspect, the gating signals, which effectively are normally supplied to the conduction controlled rectifying devices of the inverter, are blocked or inhibited from when the idle condition occurs until the desired fixed gating pattern is provided by the shift register of the control stage of the inverter. Thus, in this aspect, the inverter does not produce a moderate frequency burst of outgoing signal when the shift register cycles through and stops at the desired fixed gating pattern.