The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 1981
Filed:
Aug. 02, 1979
Benjamin T Brodie, Edmonds, WA (US);
John Fluke Mfg. Co., Inc., Mountlake Terrace, WA (US);
Abstract
A sample and hold (S/H) circuit that produces an output signal having essentially zero offset voltage error is disclosed. The S/H circuit includes a pair of operational amplifiers (OA3 and OA4) that are connected in circuit during both the sample and the hold modes of operation. In the sample mode of operation one of the operational amplifiers (OA3) receives the incoming signal through a first resistor (R1) and in accordance therewith controls the magnitude of an inverted voltage stored on a storage capacitor (C1); and, the other operational amplifier (OA4) senses the stored inverted voltage and, in accordance therewith, applies a feedback voltage to the signal input of OA3 through a second resistor (R2). In the hold mode of operation OA4 senses the voltage stored on C1 and, in accordance therewith, via R2 and OA3 controls the output voltage, which has the correct polarity due to the inverted voltage being inverted by OA3. In addition, during the hold mode of operation, the output voltage is fed back through R1 to the input of OA3 receiving the output of OA4. If the resistance of R1 equals the resistance of R2, the magnitude of the voltage stored by C1 is equal to the input signal voltage. If the resistance ratio of R2 to R1 is greater than one, the magnitude of the stored voltage is greater than the input signal voltage, even though the output voltage is equal to the input signal voltage. Storing a higher level voltage reduces the effect of capacitor leakage and OA4 drawing current from C1 on the output voltage.