Framing circuit for time multiplexed data

Abstract

A frame synchronization system for time division multiplexed data wherein all the time slots of the frame are considered during the course of the frame as opposed to being considered individually. The framing system comprises a first memory, e.g., a random access memory (RAM), and a second memory, e.g., a programmable read-only memory (ROM). The RAM includes respective locations corresponding to each relative bit time slot in the framing interval. The ROM includes respective locations corresponding to each correlation state in a predetermined sequence of states, respectively indicative of the number sequential bits in a given time slot matching the synchronization pattern. Each word in the ROM contains, in a link field, indicia of the ROM locations corresponding to the next state in the sequence. The ROM word also contains indicia of whether or not a correlation state has been attained indicative of the frame sync bit. Each RAM location is sequentially addressed in synchronism with the data input stream. The RAM output is applied, together with the data train bit, to the address input of the ROM. The contents of the RAM location corresponding to the instantaneous bit time slot provides the base address, e.g., the most significant bits, and the data bit provides the least significant bit of the address of the ROM location to be accessed. The indicia in the addressed ROM locations corresponding to the next state in sequence is fed back as a data input to the RAM and loaded into the location corresponding to the instantaneous time slot. If the state associated with the addressed ROM location indicates sufficient correlation to the predetermined sync pattern, a pulse is generated on a frame sync line during the time slot to indicate the occurrence of the framing bit. Various correlation state sequences are also described.