Combined fault current and applied voltage tripping for solid state trip

Abstract

A solid state trip circuit is disclosed which uses a shunt path saturable transformer comprised of a current transformer having a relatively high resistance shunt which serves to apply input voltage to the transformer primary winding. The larger the input current the higher the voltage drop across the shunt and the more quickly the transformer iron will become saturated. The saturation time during each half cycle then produces a measure of the current flow in the primary line. The output of the secondary winding of the transformer as well as a direct but resistive connection from the input circuit lines are applied to a solid state trip circuit which operates a circuit breaker trip latch. Energy for tripping at lower overload current is derived directly from the applied voltage from the line. At high overload conditions however, direct tripping occurs through energy derived from the transformer rather than directly from the line voltage.