The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 1981

Filed:

Aug. 14, 1979
Applicant:
Inventors:

Rainer Clemen, Boeblingen, DE;

Joerg Gschwendtner, Esslingen, DE;

Werner Haug, Boeblingen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307475 ; 307264 ; 307279 ;
Abstract

Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.


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