Incremental encoder

Abstract

A circuit for detecting each level transition of a first two-level signal of a given frequency and its leading or lagging phase relationship with a second two-level signal of said given frequency, and comprising signal level storage means having a data input terminal for receiving said first signal, a first output terminal, and a first clock pulse input terminal, and constructed to store the signal level supplied to its data input terminal and to transfer said stored signal level to its output terminal when a clock pulse is supplied to the clock pulse input terminal. First and second voltage comparator means each have a first input terminal for receiving said first and second signals, respectively, a second input terminal connected to said first output terminal and each constructed to respond to equal or non-equal signal levels supplied to their first and second input terminals to produce first and second input signals, respectively. Also provided are means responsive to the output signal of said first and second voltage comparator means to determine the leading or lagging phase relationship of said first and second signals at each level transition of said first signal, and means for supplying a clock pulse to said first clock input terminal at a predetermined time after the occurrence of each level transition of said first signal.