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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4296338 B1

PDFFull Text
Date of Patent:
Oct. 20, 1981

Filed:

May. 01, 1979

Power on and low voltage reset circuit

Applicant:
Inventor:

James S Thomas, Manor, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:

Sarli, Jr.; Anthony J.

Ingrassia; Vincent P.

Van Myers; Jeffrey

Primary Examiner:

Larry N Anagnos

Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H02J / ;
U.S. Cl.
CPC ...
307362 ; 307594 ; 307597 ; 320 48 ; 340636 ;
Abstract

An NMOS power on/low voltage reset circuit provides a substantially instantaneous reset enabling signal when a predetermined fraction of the power supply voltage falls below a predetermined reference voltage. In addition, an external capacitor is discharged. A second reset enabling signal is extended until the capacitor is again charged to a predetermined voltage thus allowing the clock oscillators of a microcomputer sufficient time to stabilize. Self test means are also provided. The reset circuit is implemented on the microcomputer chip.

Find Patent Forward Citations

Thomas, James. (1981). Power on and low voltage reset circuit (U.S. Patent No. 4296338). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4296338

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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