Electronic microprocessor system having two cycle branch logic

Abstract

An integrated chip microprocessor system has a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on such data, an instruction memory for storing a plurality of instruction words, a program counter for addressing the instruction memory, and an instruction word decoder for decoding instruction words outputted from the instruction memory for controlling the operation of the microprocessor system. The instruction word decoder has a branch decoder system for implementing a two cycle branch logic. Each program branch operation, as stored in the instruction memory has two parts: a branch instruction word which indicates a program branch and also indicates the state of a selected one of a plurality of flag latches upon which it is conditioned; and a branch address instruction word solely indicative of the instruction memory address to which the program is to branch, the branch address instruction word being stored in the next memory location in the instruction memory following the branch instruction word. The branch decoder system determines when a branch instruction word is outputted from the instruction memory and also determines if the program branch is conditional or unconditional, and if the branch is conditional, the particular state of a selected flag latch upon which the branch is conditioned. If the branch is unconditioned, or if the branch is conditional and the condition satisfied, the branch decoder system inserts the branch address instruction word which is the next instruction word outputted from the instruction memory into the program counter.