Digital servo control circuit

Abstract

In a digital servo control system, the duty cycle of a pulse width modulated signal for controlling a drive motor is determined by digital numbers representing phase and/or speed errors preset into a memory and circulating counter. The circulating counter is driven by a clock signal which performs a number of cycles during each basic timing interval. A pulse width modulated signal is initiated by a timing pulse and is terminated by each return to zero of the most significant digit of the circulating counter. The time at which the most significant digit of the circulating counter returns to zero at the end of each of its cycles is determined by the number initially preset into it. The memory is gated with the output of a four-bit counter, which increments at the same rate that the circulating counter cycles, to either lengthen each pulse width modulated signal by one clock cycle or not. The number of times the pulse-width modulated signal is lengthened in a basic timing interval is proportional to the number preset into the memory. The contents of the memory and the circulating counter are periodically changed to correspond to detected speed and/or phase errors to update the duty cycle of the pulse width modulated control signal.