The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 1981

Filed:

Feb. 29, 1980
Applicant:
Inventor:

Paul R Henneuse, San Jose, CA (US);

Assignee:

Precision Monolithics, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 45 ; 365149 ; 320-1 ;
Abstract

An improved analog track and hold circuit has a glitch-free output as the circuit switches between the tracking and the holding of an input analog signal. The circuit is of the type having a capacitor for storing an analog voltage, a transconductance amplifier for producing a charging current for the capacitor proportional to the analog voltage, a current switch for connecting and disconnecting the charging current for the capacitor, and an output circuit to buffer the capacitor voltage to the output. The improvement includes a diode array establishing first and second reference nodes across the capacitor. The diodes in the array clamp the first and second nodes to fixed incremental voltage values greater and lesser, respectively, than the capacitor voltage as the circuit tracks the analog voltage, and to fixed incremental voltage values lesser and greater, respectively, than the capacitor voltage, as the circuit holds the analog voltage. The nodes reverse their polarities by equal amounts during the switching of the circuit between the tracking and holding. In this manner, an equal and opposite voltage magnitude change is produced at each node during the switching interval, thereby preventing any net change in the capacitor voltage, and providing a glitch-free output. A special current switch gates currents through the diode array to effect the clamping.


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