Multiprocessor memory access system

Abstract

A data processing system is disclosed in which a high-speed processor is added to a slow-speed processor and in which both processors have access to a first memory unit with the slow processor having access priority over the fast processor. In order to allow the fast processor to operate without losing data when a conflict occurs during a write operation, a second memory is coupled to the fast processor in which is stored all the data stored in the first memory. When the fast processor attempts to write into both memories but fails to write into the first memory due to a conflict with the slow processor, the data stored in the second memory is then transferred to the first memory subsequent to the completion of the access operation by the slow processor. This arrangement allows the fast processor to complete the write operation interrupted by the conflicts with the slow processor, thereby allowing the fast processor and the slow processor to have access to the same data. Both memories are continuously balanced by the fast processor so that each memory will contain the same data allowing both processors access to the same data.