Arrangement for detecting the binary values of bit cells having center

Abstract

Data, in the form of a sequence of binary bits of frequency F.sub.O, is detected by deriving a clock signal H of frequency F.sub.O in response to the sequence. A level transposing device responsive to the sequence and signal H derives a bi-level signal DEI. An integrating apparatus responds to DEI to derive a signal DEINT. A decision circuit responsive to DEINT determines the polarity of signal DEINT and derives binary data bits having values that are a function of the polarity. The direction and duration of charging current supplied to a pair of capacitors of the integrator are controlled as a function of the polarity and duration of each of the levels of signal DEI, so the capacitors are respectively charged in response to even and odd numbered bits. The integrator is reset to zero at the end of the integrating operation for each level and the capacitive integrating member is supplied with a charging current proportional to F.sub.O. The voltages across the integrators are compared, by subtracting, during each bit. The polarity of the integrated difference determines the bit value, while the presence of a phase error is determined by comparing the integrated difference with a reference to derive a pair of signals indicating the polarity of the reference relative to the differences and the complement of the difference. If the difference and its complement have the same polarity relative to the reference, a phase error exists.