The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 1981

Filed:

Jul. 05, 1979
Applicant:
Inventor:

Toshiyuki Ozawa, Gunma, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03L / ;
U.S. Cl.
CPC ...
307514 ; 307528 ; 307579 ; 307246 ; 3072 / ; 331 / ; 328133 ;
Abstract

A digital phase comparator, to be used in a phase locked loop, for example, comprises a first and second input signal terminals receiving a first and second input signals, respectively, the phases of which are to be compared, and a pair of first and second delay flip-flops. The first input signal terminal is connected to a clock terminal of the first delay flip-flop and a reset or set terminal of the second delay flip-flop. The second input terminal is connected to a set or reset terminal of the first delay flip-flop and a clock terminal of the second delay flip-flop. An inverted or non-inverted output terminal of the first delay flip-flop is connected to a data terminal of the second delay flip-flop. An inverted or non-inverted output terminal of the second delay flip-flop is connected to a data terminal of the first delay flip-flop. An output signal associated with the phase difference between the first and second input signals is obtained from the output terminals of the first and second delay flip-flops.


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