Time delay and integration detectors using charge transfer devices

Abstract

An imaging system comprising a multi-channel matrix array of CCD devices wherein a plurality of sensor cells (pixels) in each channel are subdivided and operated in discrete intercoupled groups or subarrays with a readout CCD shift register terminating each end of the channels. Clock voltages are applied to the subarrays and are manipulated to selectively cause charge signal flow in each subarray in either direction independent of the other subarrays. More particularly, the array is divided into six independent subarrays, three on each side of the array, such that each channel common to three subarrays is divided into three sections of three sensor cells each. By selective application of four phase clock voltages, either one, two or all three of the sections cause charge signal flow in one direction, while the remainder cause charge signal flow in the opposite direction. This creates a form of selective electronic exposure control which provides an effective variable time delay and integration of three, six or nine sensor cells or integration stages. The device is constructed on a semiconductor sustrate with a buried channel and is adapted for front surface imaging through transparent doped tin oxide gates.