Digital timing recovery system

Abstract

An improved method of recovering a clock reference signal from digital data and maintaining small phase errors between the two. The clock reference signal is phase matched with the digital data by comparing the positive going and negative going edges of the data with the clocking edge of the clock signal. A hard decision is made on the relative phase of the clock signal and the data only after several edge transitions occur. After a finite number of samples of these transitions, a decision is made whether to advance or retard the clock signal by observing whether the majority of the data transitions over the sample period occurred prior to or after the clocking edge of the clock signal. This allows a sampled mean to be established and thereby a more accurate prediction of the relative phase between the clock signal and data to be made. In addition, a fast acquisition technique is provided to insure the clock reference signal is received in a minimum amount of time.