Method of and circuit arrangement for discharging a storage capacitor

Abstract

A storage capacitor of a sample-and-hold circuit, e.g. as used in a converter for the digitization of signal amplitudes in a PCM telephone system, is provided with a zero-setting gate comprising two parallel branches that include a first and a second transistor which are respectively saturated during a cancellation phase and a discharge phase of a resetting interval following a sampling period. The first transistor lies in series with a d-c source whose voltage substantially exceeds the maximum amplitude of signals of the same polarity to be stored on that capacitor whereby the latter acquires a charge within a range considerably narrower than the spread of positive and negative signal amplitudes. The second transistor then short-circuits the capacitor so charged, leaving a residual charge of predetermined polarity subject to still smaller variations in magnitude.