Topography for integrated circuits pattern recognition array

Abstract

An integrated circuit for sequentially receiving a plurality of digital character words produced in response to optical scanning of a bar coded label and a plurality of corresponding binary signals representing, respectively, validity, scanning direction, and timing of the digital character words includes first, second, third, and fourth sequentially located edges forming a rectangle. The integrated circuit includes input circuitry for receiving the digital character words and corresponding binary signals and further includes twelve shift registers for storing predetermined ones of the digital character words. Four frame counters and associated control circuitry responsive to the binary signals and the character words steer the incoming character words to predetermined ones of the shift registers. The integrated circuit outputs formatted character words to a digital processor system. A command decoder receiving commands from a digital processor system controls the outputting of valid, properly formatted digital character words from predetermined ones of the shift registers in response to an interrupt signal produced when a properly formatted character word is contained in one of the shift registers. The input circuitry is generally located adjacent the corner formed by the third and fourth edges. The frame counters and associated control circuitry are generally located substantially closer to the fourth edge than to the second edge. The twelve groups of shift registers are generally located between the frame state counters with their associated control circuitry and the second edge. The command decode circuitry is located adjacent the second edge.