The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 1981

Filed:

Jul. 23, 1979
Applicant:
Inventor:

Josef H Schurmann, Oberhummel, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F / ; H03G / ;
U.S. Cl.
CPC ...
330277 ; 330279 ;
Abstract

A dual gate FET has a first gate connected to receive an HF input signal and a second gate which is grounded to HF. The transistor output circuit is connected to a supply voltage terminal. A voltage divider comprising a resistor and a zener diode is connected between the supply voltage terminal and ground, the top of the voltage divider being connected to the second gate electrode. By varying the supply voltage, the amplifier gain can be adjusted. The supply voltage can be adjusted manually by a potentiometer. Alternatively, it can be adjusted automatically according to the strength of the HF input signal so that as the signal strength increases, the gain is reduced. The circuit is amenable to implementation using JFET, IGFET and MESFET transistors.


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