The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 1981

Filed:

Mar. 16, 1979
Applicant:
Inventors:

Norio Inui, Yokohama, JP;

Noriaki Kume, Kawasaki, JP;

Tetsuro Okamoto, Kawasaki, JP;

Assignee:

Fujitsu Limited, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364764 ; 364765 ; 364745 ;
Abstract

A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q.sub.1 +Q.sub.2 .times.2-n (Q.sub.1, Q.sub.2 : binary numbers). The binary numbers Q.sub.1 and Q.sub.2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q.sub.1 is used as a part of the data for performing the division processing of Q.sub.2, thus effectively transferring any error evolving during the processing of Q.sub.1 to Q.sub.2. The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.


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