The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 1981

Filed:

Apr. 26, 1979
Applicant:
Inventors:

Shintaro Hashimoto, Nara, JP;

Toshio Nishimura, Jyoyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G04B / ;
U.S. Cl.
CPC ...
364707 ; 364705 ;
Abstract

An integrated circuit device having a combined time-keeping mode and calculator mode comprises a generator stage for generating basic clock signals and system clock signals, a processor stage responsive to a supply of the system clock signals for executing arithmetic operations required for the timekeeping mode and the calculator mode key input members for introducing information into the processor stage as key input signals, and a clock control for controlling the supply of the system clock signals. The processor stage is adapted to develop a command signal to indicate the completion of the arithmetic operations. The clock control is responsive to the rising and trailing edges of the key input signals for enabling the supply of the system clock signals. The generation of the command signal causes the clock control to prevent the system clock signals from being fed to the processor stage.


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