Row selection circuits for memory circuits

Abstract

A memory subsystem includes a memory board comprising of a number of memory chips positioned at a corresponding number of physical row locations. The memory chips are one of two types selected to provide a predetermined memory capacity. The board further includes a number of decoder circuits connected to generate a corresponding number of sets of chip select signals in response to address signals applied thereto. These signals are applied through corresponding sets of logic circuits for application to the memory chips of each row. Additionally, logic gating circuits logically combine predetermined chip select signals for generating additional chip select signals. These additional chip select signals are applied through switches, the outputs of which are applied to predetermined ones of the sets of logic circuits. When the switches are positioned in a predetermined manner, the additional chip select signals are directed to only predetermined one of the physical row locations via the sets of logic circuits. In this case, only the predetermined row locations are populated with one of the types of memory chips of much larger capacity. This provides the same predetermined memory capacity that is provided when all of the physical row locations are populated with the other type of memory chips of smaller capacity making possible reductions in manufacturing costs.