Spark timing control circuit for controlling the timing of spark

Abstract

A spark timing control circuit for an internal combustion engine, includes a speed band selector circuit which responds to an electrical signal indicative of engine speed and provides an output signal indicative of which of a plurality of speed bands is occupied by the engine speed. Spark timing information for each speed band is stored in a memory as a first word in units of angular rotation of the engine for the heaviest engine operating load, and a second and third words indicative of the slope of straight line approximations to the curve of engine load plotted against advance in said angle units. A build up circuit responds to an electrical signal indicative of the engine operating load and computes from the second and third words a build up word which is added to the first word in an accumulator so as to derive an accumulated word in said angle units indicative of the desired spark timing. A residue angle counter, clocked by angle clock pulses from a clock converts the accumulated word into a corresponding time delay which is used to control the timing of the occurrence of spark ignition.