The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 1981
Filed:
Jun. 27, 1979
Ying K Shum, Cupertino, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An electrically erasable floating gate storage cell (EPROM) is disclosed which comprises a body of single crystal silicon semiconductor material having a substrate of one conductivity type, a source region and a drain region each of a second conductivity type, a channel region of the first conductivity type connecting the source region and drain region, a polycrystalline silicon layer conductively connected to either the source region or the drain region, a conductive insulated floating gate which partially overlies and is separated from the polycrystalline silicon layer by a layer of silicon dioxide and a control gate which overlies and is separated from the floating gate by a layer of silicon dioxide. Fowler-Nordheim tunneling current occurs between the polycrystalline layer and the floating gate during programming and erasing of the EPROM. The floating gate influences the conductivity of the channel region in accordance with the charge stored thereon during programming. The control gate is oriented over the entire channel region to control the conductivity of the channel region in accordance with voltages applied thereto during operation of the EPROM.