The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 1981

Filed:

Dec. 04, 1978
Applicant:
Inventors:

Ingrid E Magdo, Hopewell Junction, NY (US);

Steven Magdo, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B44G / ;
U.S. Cl.
CPC ...
156628 ; 156643 ; 156644 ; 156657 ; 156662 ; 2041 / ; 118504 ; 428134 ; 428137 ; 428156 ;
Abstract

In the fabrication of semiconductor integrated circuits, a method is provided for forming a self-supporting silicon mask and a further method is provided for utiliziing such a self-supporting separable silicon mask to perform various masking steps in the integrated circuit fabrication. The mask is formed by forming, at a surface of a planar silicon substrate, a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath the layer, applying to selected portions of the other surface of the substrate an etchant which preferentially etches silicon having lower concentrations of conductivity-determining impurities to thus etch out preferentially selected portions of the substrate to form at least one recess extending through the substrate to said silicon layer, and then etching from the surface of said silicon layer opposite the substrate recess to form patterns of openings extending through the silicon layer to said substrate recess. The seperable self-supporting silicon mask thus formed is then placed on the surface of an integrated semiconductor circuit member so that the opposite surface of the silicon layer interfaces with the integrated circuit member surface. Then, the masked semiconductor member may be subjectd to any conventional integrated circuit fabrication step which alters the characteristics of the portions of said member surface exposed in said pattern of mask openings; such fabrication steps include introduction of impurities, etching as well as lift-off deposition of metallic and non-metallic patterns. Upon the completion of the step or steps, the self-supporting silicon mask is separated from the integrated circuit member.


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