The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 1981
Filed:
Feb. 09, 1979
Applicant:
Inventor:
Philip J Baun, Jr, Andover, MA (US);
Assignee:
Bell Telephone Laboratories, Incorporated, Murray Hill, NJ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 49 ; 307216 ;
Abstract
A parity circuit (FIG. 6) for n signals comprises n-1 parity building blocks (61-67) connected in a parity tree configuration. Each parity building block comprises three interconnected NAND gates (41-43). A first pair of signal inputs (A and B) are connected to the input of the first and second NAND gates (41 and 42), and a second pair of signal inputs (C and D) are connected to the input of the first and third NAND gates (41 and 43). The output of the first NAND gate (41) is coupled to the input of the second and third NAND gates (42 and 43). The pairs of inputs are controlled so that at least one signal in each pair is high ('1').