The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 1981

Filed:

Feb. 09, 1979
Applicant:
Inventor:

Jurgen Knodler, Remshalden-Grunbach, DE;

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
F02P / ;
U.S. Cl.
CPC ...
324384 ; 324169 ; 324386 ; 324392 ;
Abstract

To permit tests of: ignition timing; dwell angle; engine speed; and voltage levels, a pulse train is provided derived from the ignition system of the engine; the pulse train is applied to a frequency multiplier, preferably a phase locked loop (PLL) which provides a sequence of output pulses having a pulse repetition rate which is a multiple of the frequency of the signals or pulses of the pulse train. An AND gate has the multiplied signals applied thereto and is enabled, selectively, in accordance with the desired test. The output of the AND gate is applied to a counter which counts multiplied pulses within the interval of enabling of the AND gate, the output being applied to a digital indicator to provide a direct readable digital output; preferably, the multiplication rate is selected to provide a digital output indication which is directly readable in desired units. To determine dwell angle, enabling pulses are applied to the AND gate from the ignition system; to determine spark timing, derived enabling pulses are applied to the AND gate, derived from the ignition system upon being compared with a reference signal, for example an upper dead center (TDC) signal; to determine speed, the enabling pulses are applied with respect to a clock reference; and to determine a voltage test level, the input to the system is disconnected and the test voltage applied to a voltage controlled oscillator of the PLL.


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