Cache arrangement utilizing a split cycle mode of operation

Abstract

A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive address signals from a plurality of address sources. The system further includes a directory organized into a plurality of levels for storing address information required for accessing blocks from the cache storage unit and timing circuits for defining first and second halves of a cache cycle of operation. Control circuits coupled to the timing circuits generate control signals for controlling the operation of the address selection switch. During the previous cycle, the control circuits condition the address selector switch to select an address which is loaded into the address register during the previous half cycle. This enables either the accessing of instructions from cache or the writing of data into cache during the first half of the next cache cycle. During the first half of the cycle, the address selected by the address switch in response to control signals from the control circuits is clocked into the address register. This permits processor operations, such as the accessing of operand data or the writing of data into cache to be performed during the second half of the same cycle.