The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 1981

Filed:

Feb. 26, 1979
Applicant:
Inventors:

Carleton D Driscoll, Cary, NC (US);

James N Hobbs, Jr, Cary, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06M / ; H02H / ;
U.S. Cl.
CPC ...
235 / ; 235 / ; 340663 ; 361 92 ; 364900 ;
Abstract

A power line disturbance (PLD) detector circuit includes a digital counter which is driven by pulses provided by a clock in an associated data processing system. The PLD detector circuit includes a comparator amplifier for comparing primary AC power to a DC reference voltage on a cycle-by-cycle basis. The amplifier generates a reset pulse once during each AC cycle as long as the AC voltage exceeds the DC reference voltage. When a decoder circuit detects a count outside the range of counts attained by the digital counter between normally occurring reset pulses, the decoder circuit responds by generating a PLD signal. The PLD signal is provided both to the associated data processing system and to a Power On Reset circuit. The Power On Reset circuit is initialized by the PLD signal, permitting the circuit to respond consistently upon subsequent restoration of power.


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