The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 1981
Filed:
Oct. 16, 1978
Akira Misawa, Tokyo, JP;
Tatsuo Numata, Tokyo, JP;
Pioneer Electronic Corporation, Tokyo, JP;
Abstract
A PLL tuning device in a receiver uses a digital memory board and array of photo-transistors scanning the memory board for station selection. When the transistors are lined up with a column, a digital output is fed to a switching device and to a programmable frequency divider. Muting action is released when the output is delivered to the divider, but, when the array is between columns, muting action takes place. In one embodiment, the photo-transistor output is fed to a latch and to an OR gate serving as the switch. A one-shot is triggered in response to the setting of the OR gate at an H level. Digital information is fed to the programmable frequency divider from the latch until the one-shot is fired. In another embodiment, the latch and one-shot are eliminated. Photo-transistor output is fed to both an OR gate and the frequency divider. The OR gate controls a switch that closes muting switches only when information is being generated by the photo-transistors. However, when the sensor array is between signals the tuner is maintained in a muted state.