The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 1980

Filed:

Aug. 18, 1978
Applicant:
Inventor:

Se June Hong, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; G01R / ;
U.S. Cl.
CPC ...
324 / ; 324 51 ; 371 25 ;
Abstract

This specification describes the testing of interconnections between modules mounted on a card and between the modules and the input and output terminals of the card. Each of the modules has an Exclusive-OR circuit which receives an input from each of the input pins of the module and has a single output which is taken off an output pin of the module. Also, each of the modules has a test input circuit for accessing all of the output pins of the module in parallel from a single input terminal. The test input circuits are used to apply a binary 0 followed by a binary 1 to all the outputs of all the modules. The Exclusive-OR circuits are used to monitor the response to those signals. By testing in this manner, all the connections between the modules and also between the modules and the card terminals can be checked for stuck ones and zeros. In the preferred embodiment a more complex but still relatively simple bit pattern can test all the interconnection nets to determine if there are shorts between any of the nets.


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