Crt display terminal priority interrupt apparatus for generating

Abstract

A cathode ray tube display terminal system includes a central processor subsystem and a number of certain peripheral subsystems all of which are coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request signals from certain of the peripheral subsystems and on a predetermined priority basis modifies an address generated by the central processor subsystem in dependence upon which of the requesting certain peripheral subsystems has the highest priority. The modified address, called a vectored address points to a firmware subroutine stored in a memory subsystem which is also coupled to the system bus and which processes the interrupt from the highest priority cetain peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single interrupt signal which is also applied to the apparatus in the central processor system. The highest priority other peripheral subsystem generating the single interrupt signal responds to an interrupt acknowledge signal from the central processor subsystem by sending address signals to the apparatus which are used to modify the address generated by the central processing subsystem so as to produce the vectored address.