The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 1980

Filed:

Apr. 19, 1979
Applicant:
Inventors:

Thomas P Redfern, San Jose, CA (US);

Thomas M Frederiksen, San Jose, CA (US);

Joseph J Connolly, Jr, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365 96 ; 365104 ;
Abstract

A read only memory is fabricated using metal oxide semiconductor technology and is intended for incorporation into large scale integrated circuits. A plurality of memory transistors is arrayed in a configuration having columns, each of which is associated with an address line, and rows, each of which is associated with a word line. A memory transistor is located at each intersection of an address line and a word line. Each memory transistor represents a bit location and includes a severable conductive link coupled in series and located on top of the field oxide surrounding the memory transistors. Each memory transistor in a particular column has its gate coupled to an address line. Each memory transistor in a particular row completes a series circuit which includes the severable conductive link between a first power supply terminal and a word line. Each word line includes a resistor coupled to the other power supply terminal. When a particular column is addressed, and the associated transistors in the address line turned on, all of the bits in the associated word will be 'ones.' The memory is programmed as desired after circuit manufacture in the wafer die sort operation by severing selected links with a laser beam. The severed device will program a 'zero' into the bit location. The word lines are coupled to a decoder that employs an array of gates having input pairs, one of which displays hysteresis. The memory also includes an external program simulation circuit which permits externally generating a particular digital word to simulate the memory content prior to programming.


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