The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 1980

Filed:

Jun. 19, 1979
Applicant:
Inventors:

Yoichi Nakashima, Hitachi, JP;

Yosikazu Takita, Hitachi, JP;

Sousi Suzuki, Hitachi, JP;

Katsumi Akabane, Hitachi, JP;

Michihiro Misawa, Hitachi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 39 ; 357 38 ; 357 55 ; 357 58 ; 357 86 ; 357 90 ;
Abstract

A semiconductor substrate comprises at the central portion a diode region which includes a P-type base layer, an N-type low impurity concentration layer and an N-type base layer and at the outer peripheral portion a thyristor region which includes an N-type emitter layer, a P-type base layer, an N-type low impurity concentration layer, an N-type base layer and a P-type emitter layer. The P-type base layer and the N-type emitter layer are in contact with a cathode electrode, the N-type base layer and the P-type emitter layer are in contact with an anode electrode, and the diode and thyristor regions are connected in anti-parallel. Contiguous to the outer periphery of the N-type base layer interposed between the N-type low impurity concentration layer and the P-type emitter layer is formed an N-type high impurity concentration region higher in impurity concentration than the N-type base layer. The N-type high impurity concentration region limits spreading of a depletion layer which is created when a forward voltage is applied to the thyristor region.


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