Method and apparatus for generating timing phase error signals in psk

Abstract

A circuit arrangement for combining a measure of the single phase error for a received data signal in a PSK demodulator with a measure of the direction of rotation of the receive data signal phasor between adjacent sample times for producing a timing phase error signal for controlling the phase of a local clock timing signal in the demodulator. In a demodulator producing a digital word defining differences between the phases of decoded phasors at adjacent sample times, a binary bit D.sub.k of the digital word may define the direction of rotation of the received signal phasor between the adjacent sample times. Sample values of the signal phase error signal in the demodulator are quantized into single binary bits E.sub.k indicating the sense of the signal phase error at sample times. In one circuit arrangement, binary bits E.sub.k and D.sub.k are combined in an exclusive-OR gate for producing a binary timing phase error bit M.sub.k. In a demodulator where phase differences are consecutively numbered clockwise in straight binary, the output of the exclusive-OR gate is inverted for producing binary timing phase error bits M.sub.k. In another circuit arrangement, binary bits A.sub.k and B.sub.k indicating the sense of the in-phase and quadrature-phase signal components for decoded phasors at a number of sample times are logically combined with signal phase error bits E.sub.k for producing binary timing phase error bits M.sub.k at sample times.